In general, two different types of devices have been used for the photo-detection in the charge domain in the past: the first type is a pinned photodiode (PPD) (see, e.g., Nobukazu Teranishi et al, “No image lag photodiode structure in the interline CCD image sensor”, IEEE, 1982), which is available today in most complementary metal-oxide semiconductor (CMOS) process technologies, and the second type use MOS gate structures, which may be fabricated in CMOS technology or in an optimized charge-coupled device (CCD) technology.
A pinned photodiode generally has two implants in the substrate, the doping concentrations of which are chosen in such a way that a fully depleted area is created beneath a very shallow non-depleted layer at the substrate surface. With reference to FIG. 1, if the substrate 12 is supposed to be p-doped, the two implant steps comprise a deep n− implant 14 and a shallow p+ implant 16, where the p+ extends laterally beyond the n− layer in order to create an electrical connection to the substrate 12. At one side of the structure, a poly-silicon gate 18 is placed that enables the transfer of the charges out of the PPD region 14 to a sense node diffusion 20. The region around the so-called transfer gate as well as the gate itself is usually optimized with regard to the charge transport process. The pinned region 14 defines the photo-sensitive area 24 where photons are converted into electric charges. As long as the transfer gate 18 is set to low potential, then the photo-generated charges are stored within the PPD region 14.
With reference to FIG. 2, MOS gate structures usually apply a poly-silicon gate 22, which should be generally photo-transparent at least for the wavelength of interest or at least long wavelengths >500 nanometers (nm). Photons create electric charges in the area 24 of the substrate 12 beneath the gate 22 where they may be stored unless the adjacent transfer gate 18 opens the channel either to another storage gate region or to a sense node 20, as shown. While the sense node 20 is typically integrated in each pixel separately when using CMOS processes, there is only one sense node and several storage and shift registers when using CCD technology. However, the principle of the photo-sensitive element is the same in either case.
Both types of charge domain photo-detection devices have the same drawbacks in terms of the charge handling. If the charge needs to be transferred from one photo-detecting element to another storage or sense region, the efficiency of this kind of transport process is highly dependent on the electric fields supporting this process. In extreme conditions, which are particularly the case for larger pixel sizes of, for example, greater than 1 micrometer, the photo-detecting regions do not exhibit effective lateral electric fields supporting the charge transport towards the sense node. This situation is depicted in FIG. 3 for the case that the transfer gate is set to high potential level. Due to a flat potential distribution within the sensitive region 24, single electric charges are transported to the sense node 20 by thermal movement processes, which may be some orders of magnitude slower than charge movement due to electric fields.
A first solution to accelerate the charge transport has been disclosed in U.S. Pat. No. 8,299,504 B2 by Seitz. A single high-resistive gate creates a lateral drift field by a current flowing through the gate itself. This approach has been verified in practice. However, large pixel arrays consume significant amount of power due to the permanent resistive losses plus additional capacitive losses when being operated in a dynamic mode of operation.
Another possible solution to accelerate the charge transport has been disclosed in U.S. Pat. No. 8,115,158 B2 by Buettgen, which is incorporated herein by this reference in its entirety.
As shown in FIG. 4, instead of a single gate across the photo-sensitive area, several adjacent gates 22-1 to 22-n are used to form a gate chain of small and narrow gates above the photosensitive area 24. By applying increasing voltages on the gates 22-1 to 22-n, a potential distribution as shown in FIG. 5 is generated. This method has proven its efficiency in practice. Compared to the method of U.S. Pat. No. 8,115,158 B2 no permanent power consumption is expected.
The potential distribution with the semiconductor material 12 ideally looks as shown in the FIG. 5. The potential increase between two gates is ideally positive. However, this depends on the potential steps applied between adjacent gates 22 and the space between two gates 22-x and 22-(x+1). The closer the gates are located to each other, the more unlikely is the generation of any potential bumps between two gates. That is the reason why in CCD processes overlapping gate structures are used where the gate-to-gate distances are typically in the nanometer range.
Concerning the PPD pixel several approaches have been studied to accelerate the charge transport. The first example consists of a shaping of the n− implant layer in order to achieve a kind of pinning voltage modulation over space. This is described in Cedric Tubert et al, “High Speed Dual Port Pinned-photodiode for Time-of-Flight Imaging”, IISW, 2009. Another approach exploits a spatial pinning voltage modulation by applying a doping gradient for the n− implant. This is presented for example in A. Spickermann et al, “CMOS 3D image sensor based on pulse modulated time-of-flight principle and intrinsic lateral drift-field photodiode pixels”, ESSCIRC, 2011.
All PPD-based methods have as common drawback: the total inflexibility in terms of drift voltage control compared to the gate-based approaches because the pinning voltages are pre-determined by the doping concentrations and cannot be controlled from external source. This makes PPD pixels unattractive in many applications. Concerning the speed enhancement approaches, any spatial modulation of the pinning voltage goes hand in hand with a modulation of the sensitivity as well. Minimization of potential bumps and step-wise approximations of ideal potential distribution functions are an important concern. Special graymasks or several implant steps must be supplied by the foundry, which is rather unusual for standard imaging processes.
Regarding the gate-based approaches, special requirements to the processing technologies are set here as well: very high resistive gate must be used to hold the power consumption as low as possible, or narrow gate gaps or even overlapping gates are necessary in order to avoid potential bumps between adjacent gates. The discretization of the potential gradient by the use of several gates always leads to a step function but never to a perfect constant gradient.